1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and its fabrication method, and more particularly, to an LCD device and its fabrication method capable of simplifying a fabrication process and enhancing yield by reducing the number of masks used for fabrication of a polycrystalline silicon thin film transistor.
2. Description of the Related Art
Recently, as research and development of information displays and demand for using a portable (mobile) information medium increase, research on and commercialization of a light thin film type flat panel display (FPD) which can substitute for the existing display device CRT are actively ongoing.
Of the FPDs, in particular, an LCD, a device for producing an image by using the optical anisotropy of liquid crystal, exhibits excellent resolution, color display and picture quality, so it is popular in notebook computers, desktop monitors or the like.
The liquid crystal display panel includes a color filter substrate, namely, a first substrate, an array substrate, namely, a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.
As a switching device of the liquid crystal display device, the thin film transistor (TFT) is used, and as a channel layer of the TFT, an amorphous silicon thin film or a polycrystalline silicon thin film is used.
In a process for fabricating the LCD device, a plurality of masking processes (namely, photolithography process) are required for fabricating the array substrate including the TFT, so a method for reducing the number of masking processes is on demand in terms of productivity.
The structure of the general LCD device will now be described with reference to FIG. 1.
FIG. 1 is a plan view illustrating a portion of an array substrate of the general LCD device. Although actual array substrate includes the M×N number of pixels as the N number of gate lines and the M number of data lines cross each other, only one pixel is illustrated in FIG. 1 for the sake of explanation.
As illustrated, a gate line 16 and a data line 17 are arranged vertically and horizontally on an array substrate 10, defining a pixel region. A TFT as a switching device is formed at the crossing of the gate line 16 and the data line 17. A pixel electrode 18 is formed at each pixel region.
The TFT includes a gate electrode 21 connected to the gate line 16, a source electrode 22 connected to the data line 17 and a drain electrode 23 connected to the pixel electrode 18. The TFT also includes a first insulation film (not illustrated) and a second insulation film (not illustrated) for insulating the gate electrode 21 and source/drain electrodes 22 and 23, and an active pattern 24 for forming a conductive channel between the source electrode 22 and drain electrode 23 by a gate voltage supplied to the gate electrode 21.
Through the first contact hole 40A formed at the first and second insulation films, the source electrode 22 is electrically connected with a source region of the active pattern 24 and the drain electrode 23 is electrically connected with a drain region of the active pattern 24.
A third insulation film (not illustrated) having a second contact hole 40B is formed on the drain electrode 23, so that the drain electrode 23 and the pixel electrode 18 are electrically connected through the second contact hole 40B.
The process of fabricating the array substrate constructed as described will now be explained with reference to FIGS. 2A to 2F.
FIGS. 2A to 2F are sequential sectional views of the process for fabricating the array substrate of FIG. 1 taken along line I-I′. The illustrated TFT is a polycrystalline silicon TFT which uses polycrystalline silicon as a channel layer.
As illustrated in FIG. 2A, the active pattern 24 is formed as a polycrystalline silicon thin film on the substrate 10 by using a photolithography process (a first masking process).
Next, as illustrated in FIG. 2B, a first insulation film 15A and a conductive metal material are sequentially deposited on the entire surface of the substrate 10 with the active pattern 24 formed thereon, and then, the conductive metal material is selectively patterned by using the photolithography process (a second masking process) to form the gate electrode 21 over the active pattern 24 with the first insulation film 15A interposed therebetween.
Thereafter, p+ type or n+ type source/drain regions 24A and 24B are formed at certain regions of the active pattern 24 by injecting a high density impurity ion by using the gate electrode 21 as a mask. The source/drain regions 24A and 24B are formed for ohmic contact with source/drain electrodes (to be described).
And then, as illustrated in FIG. 2C, a second insulation film 15B is deposed on the entire surface of the substrate 10 with the gate electrode 21 formed thereon, and then, a portion of the first and second insulation films 15A and 15B is removed through the photolithography (a third masking process) to form the first contact hole 40A exposing a portion of the source/drain regions 24A and 24B.
Subsequently, as illustrated in FIG. 2D, a conductive metal material is deposited on the entire surface of the substrate 10 and then patterned by using the photolithography process (a fourth making process) to form the source electrode 22 connected with the source region 24A and the drain electrode 23 connected with the drain region 24B through the first contact hole 40A. In this case, a portion of the conductive metal layer constituting the source electrode 22 extends in one direction to form the data line 17.
And then, as illustrated in FIG. 2E, a third insulation film 15C is deposited on the entire surface of the substrate 10, and then, a second contact hole 40B is formed, exposing a portion of the drain electrode 23 by using the photolithography process (a fifth masking process).
Finally, as illustrated in FIG. 2F, a transparent conductive metal material is deposited on the entire surface of the substrate 10 with the third insulation film 15C formed thereon and then patterned by using the photolithography process (a sixth masking process) to form a pixel electrode 18 connected with the drain electrode 23 through the second contact hole 40B.
As mentioned above, in fabricating the array substrate including the polycrystalline silicon TFT, a total of six photolithography processes are required to pattern the active pattern, the gate electrode, the first contact hole, the source/drain electrodes, the second contact hole and the pixel electrode.
The photolithography process is a process of transferring a pattern formed on a mask onto the thin film-deposited substrate to form a desired pattern, including a plurality of processes such as applying a photosensitive solution, exposing and developing process. As a result, the plurality of photolithography processes degrade a production yield and cause a high possibility that a fabricated TFT is defective.
In particular, the mask designed to form the pattern is expensive, so the increase in the number of masks applied to the process would lead to an increase in a fabrication cost proportionally.